1. Field
The present disclosure relates generally to a layout construction, and more particularly, to a structure for stacking common gate fin field-effect transistors (FinFETs) for area optimization.
2. Background
A standard cell is an integrated circuit that may be implemented with digital logic. An application-specific integrated circuit (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cells. Reducing a size/area footprint of ASICs is beneficial. Accordingly, there is a need for reducing the size/area footprint of individual standard cells.